The present invention relates to a highly reliable high-speed semiconductor integrated circuit which can be operated with low power consumption for realizing a fine metal-oxide-semiconductor (MOS) type semiconductor device.
In order to realize a very large-scale integrated circuit (VLSI) having even higher integration, the size of a MOS type semiconductor device usable for such a VLSI has been reduced more and more in recent years. As a result, currently available devices are formed with a minimum size in a half-micron region or in a sub-half micron region. However, if a device having such a fine size is formed, the electric characteristics of such a device are likely to be degraded because of a short-channel effect or a hot-carrier effect, thereby seriously influencing the reliability of the device.
On the other hand, in order to develop VLSI technologies satisfactorily applicable in the expanding multi-media society, a semiconductor device must realize not only high-speed operation but also low power consumption.
In order to improve the resistance of a device to the degradation caused by a hot-carrier effect or a short-channel effect and to improve the drivability thereof, a MOS type semiconductor device having an asymmetric impurity profile in the channel has been suggested. Such a MOS semiconductor device is described, for example, by T. Matsui et al. in 1991 Symposium on VLSI Technology, pp. 113-114, in which a laterally-doped channel (LDC) structure is disclosed.
FIG. 14 is a cross-sectional view showing a MOS type semiconductor device having an LCD structure.
The semiconductor device includes: an n-type high-concentration source diffusion layer 2 and an n-type high-concentration drain diffusion layer 3 which are formed in a semiconductor substrate 1; a gate oxide film 4 formed on the semiconductor substrate 1; a gate electrode 5 formed on the gate oxide film 4; and a p-type high-concentration diffusion layer 6 provided in a channel region between the source diffusion layer 2 and the drain diffusion layer 3 and under the source diffusion layer 2 in the semiconductor substrate 1. The p-type diffusion layer 6 is characterized in that the impurity concentration thereof monotonically decreases from the source side to the-drain side. In this structure, by setting the impurity concentration on the source side of the p-type diffusion layer 6 to be high, it is possible to improve the resistance of the device to the short-channel effect. In addition, by setting the impurity concentration on the drain side of the p-type diffusion layer 6 to be low, it is possible to reduce a high electric field generated in the vicinity of the drain, thereby suppressing the generation of hot carriers. Therefore, a conventional lightly-doped drain (LDD) structure is not required for this semiconductor device, thereby realizing high drivability.
However, this structure is not suitable for a MOS type semiconductor device to be formed in a region having a size on the order of a quarter micron or less. This is because, the MOS type semiconductor device having the LDC structure shown in FIG. 14 has the following problems.
(1) A p-type high-concentration diffusion layer is provided under a source diffusion layer and the impurity concentration in the p-type diffusion layer is as high as 1xc3x971018 cmxe2x88x923 or more in order to suppress the short-channel effect. As a result, the parasitic capacitance of the p-n junction between the source and the substrate is adversely increased as compared with a conventional structure. In general, the speed of a MOS type semiconductor device is proportional to the product obtained by multiplying together an inverse of a saturated current value and a load capacitance. Therefore, if such a semiconductor device having a large parasitic capacitance in the p-n junction between the source and the substrate, as in the case of a semiconductor device having a LDC structure, is applied to a circuit such as a NAND type CMOS circuit in which a voltage is applied to a region between the source and the substrate, the speed of the device is adversely decreased. On the other hand, the power consumed by a MOS type semiconductor device is proportional to the product obtained by multiplying together the load capacitance and the square of the applied voltage. Therefore, the power consumption of the circuit is adversely increased.
(2) The p-type diffusion layer for controlling the threshold voltage and suppressing the short-channel effect reaches the surface of the substrate and the impurity concentration on the source side of the channel region is as high as 1xc3x971018 cmxe2x88x923 in the vicinity of the surface of the substrate. As a result, the mobility of the carriers is considerably decreased on the source side because of the scattering of the impurity. Since the current value of a MOS type semiconductor device is determined by the behavior of the carriers on the source side, the saturated current value is decreased.
(3) When a device having a size on the order of a quarter micron or less is formed, the threshold voltage is decreased and the device becomes seriously affected by the short-channel effect. The short-channel effect depends upon an effective channel length and a junction depth between the source diffusion layer and the drain diffusion layer. Since a LDC structure has a deep junction depth between the source diffusion layer and the drain diffusion layer, the decrease in the threshold voltage cannot be suppressed in a region having a size on the order of a quarter micron or less.
(4) In fabricating a semiconductor device having a LDC structure, an additional process step of masking the drain electrode is necessary when a p-type diffusion layer is formed on the source side.
Because of the above-described reasons, a highly reliable high-speed semiconductor device cannot be formed in a region having a size on the order of a quarter micron or less according to the conventional technologies for forming a MOS type semiconductor device.
The MOS type semiconductor device of the invention includes: a semiconductor substrate of a first conductivity type; a first source diffusion layer of a second conductivity type formed in a principal surface region of the semiconductor substrate; a first drain diffusion layer of the second conductivity type formed in the principal surface region of the semiconductor substrate so as to be distant from the first source diffusion layer; a channel region formed in the semiconductor substrate so as to be located between the first source diffusion layer and the first drain diffusion layer; a gate insulating film provided on the channel region.; a gate electrode provided on the gate insulating film; and an impurity diffusion layer of the first conductivity type which is formed in the channel region, and has a nonuniform impurity concentration profile along a channel length direction, an impurity concentration in a region of the impurity diffusion layer which is adjacent to the first source diffusion layer being higher than an impurity concentration in a region of the impurity diffusion layer which is closer to the first drain diffusion layer. In the semiconductor device, an impurity concentration of the semiconductor substrate just under the first source diffusion layer is lower than an impurity concentration on a source side of the impurity diffusion layer of the first conductivity type.
In one embodiment, the impurity diffusion layer of the first conductivity type includes a surface diffusion layer of the first conductivity type provided in a surface region of the channel region.
In another embodiment, the MOS type semiconductor device further includes a pair of second source/drain diffusion layers of the second conductivity type which are formed in both end portions of the channel region. In the semiconductor device, the pair of second source/drain diffusion layers of the second conductivity type have an impurity concentration of 1xc3x971019 cmxe2x88x923 or more and have a junction depth shallower than a junction depth of the first source/drain diffusion layers.
In still another embodiment, the MOS type semiconductor device further includes a pair of second source/drain diffusion layers of the second conductivity type which are formed in both end portions of the channel region. In the semiconductor device, the pair of second source/drain diffusion layers of the second conductivity type have an impurity concentration of 1xc3x971019 cmxe2x88x923 or more and have a junction depth shallower than a junction depth of the first source/drain diffusion layers.
In still another embodiment, the first source/drain diffusion layers extend to regions under both end portions of the gate electrode, respectively.
In still another embodiment, the MOS type semiconductor device further includes a pair of impurity diffusion layers of the first conductivity type which are formed under the second source/drain diffusion layers so as to be in contact with a side portion of the first source diffusion layer and a side portion of the first drain diffusion layer, respectively.
According to another aspect of the present invention, a method for fabricating a MOS type semiconductor device is provided. The method includes the steps of: sequentially depositing a first insulating film and a conductive film to be used as a gate electrode on a semiconductor substrate of a first conductivity type, thereby forming a multi-layered film; selectively etching a predetermined portion of the multi-layered film until the first insulating film is exposed, thereby forming the gate electrode; and implanting ion seeds of the first conductivity type by using the gate electrode as a mask, thereby forming a diffusion layer for controlling a threshold potential.
In one embodiment, the ion seeds are implanted into the semiconductor substrate during the ion implantation step in a direction which is parallel to a plane including a line vertical to a principal surface of the semiconductor substrate and a line extending along a channel length direction, and is inclined by seven degrees or more with respect to the line vertical to the principal surface of the semiconductor substrate.
In another embodiment, the ion seeds are implanted into the semiconductor substrate during the ion implantation step in a direction which is parallel to a plane including a line vertical to a principal surface of the semiconductor substrate and a line extending along a channel length direction, and is inclined by seven degrees or more with respect to the line vertical to the principal surface of the semiconductor substrate, thereby making nonuniform along the channel length direction an impurity concentration of the diffusion layer for controlling a threshold potential.
In still another embodiment, the method for fabricating a MOS type semiconductor device includes the steps of: implanting ion seeds of a second conductivity type by using the gate electrode as a mask, thereby forming second source/drain diffusion layers of the second conductivity type; depositing a second insulating film on the semiconductor substrate and the gate electrode; anisotropicly etching the second insulating film so as to leave the second insulating film on sides of the gate electrode; and implanting ion seeds of the second conductivity type by using the gate electrode and the second insulating film as a mask, thereby forming first source/drain diffusion layers of the second conductivity type.
In still another embodiment, the method for fabricating a MOS type semiconductor device includes the steps of: implanting ion seeds of the first conductivity type into the semiconductor substrate by using the gate electrode as a mask in a plane which is vertical to a principal surface of the semiconductor substrate and is parallel to a channel length direction, and is inclined by seven degrees or more with respect to a line vertical to the principal surface of the semiconductor substrate, thereby forming an asymmetric diffusion layer of the first conductivity type for controlling a threshold potential; implanting ion seeds of the second conductivity type into the semiconductor substrate in a plane which is vertical to the principal surface of the semiconductor substrate and is parallel to the channel length direction, and is inclined by seven degrees or more with respect to the line vertical to the principal surface of the semiconductor substrate, thereby forming second source/drain diffusion layers of the second conductivity type; depositing a second insulating film on the semiconductor substrate and the gate electrode; anisotropicly etching the second insulating film so as to leave the second insulating film on sides of the gate electrode; and implanting ion seeds of the second conductivity type by using the gate electrode and the second insulating film as a mask, thereby forming first source/drain diffusion layers of the second conductivity type having a junction depth deeper than a junction depth of the second source/drain diffusion layers. In this method, the ion implantation step of forming the second source/drain diffusion layers is performed so that an implant dose from the source side is larger than an implant dose from the drain side and that the second source/drain diffusion layers have an asymmetric concentration profile.
The MOS type semiconductor device according to still another aspect of the present invention includes: a semiconductor substrate of a first conductivity type; a first source diffusion layer of a second conductivity type formed in a principal surface region of the semiconductor substrate; a first drain diffusion layer of the second conductivity type formed in the principal surface region of the semiconductor substrate so as to be distant from the first source diffusion layer; a channel region formed in the semiconductor substrate so as to be located between the first source diffusion layer and the first drain diffusion layer; a gate insulating film provided on the channel region; a gate electrode provided on the gate insulating film; a second source diffusion layer of the second conductivity type which is formed between the first source diffusion layer and the first drain diffusion layer, is in contact with the first source diffusion layer and the principal surface of the semiconductor substrate, and has a junction depth shallower than a junction depth of the first source diffusion layer; and a second drain diffusion layer of the second conductivity type which is formed between the first source diffusion layer and the first drain diffusion layer, is in contact with the first drain diffusion layer and the principal surface of the semiconductor substrate, and has a junction depth shallower than a junction depth of the first drain diffusion layer. In the semiconductor device, a length of the second source diffusion layer of the second conductivity type along a channel length direction is shorter than a length of the second drain diffusion layer of the second conductivity type along the channel length direction.
In one embodiment, an impurity concentration of the second source diffusion layer and the second drain diffusion layer of the second conductivity type is 1xc3x971019 cmxe2x88x923 or more.
In another embodiment, the MOS type semiconductor device further includes an impurity diffusion layer of the first conductivity type which is formed in the channel region, and has a nonuniform impurity concentration profile along a channel length direction, an impurity concentration in a portion of the impurity diffusion layer which is adjacent to the first source diffusion layer being higher than an impurity concentration in a portion of the impurity diffusion layer which is closer to the first drain diffusion layer. In the semiconductor device, an impurity concentration of the semiconductor substrate just under the first source diffusion layer is lower than an impurity concentration on a source side of the diffusion layer of the first conductivity type.
According to still another aspect of the present invention, a method for fabricating a MOS type semiconductor device is provided. The method includes the steps of: sequentially depositing a first insulating film and conductive film to be used as a gate electrode on a semiconductor substrate of a first conductivity type, thereby forming a multi-layered film; selectively etching a predetermined portion of the multi-layered film until the first insulating film is exposed, thereby forming the gate electrode; implanting ion seeds of a second conductivity type by using the gate electrode as a mask, thereby forming first source/drain diffusion layers of the second conductivity type; forming side wall spacers on sides of the gate electrode; implanting ion seeds of the second conductivity type from a source side into the semiconductor substrate by using the gate electrode and the side wall spacers as a mask in a plane including a line vertical to a principal surface of the semiconductor substrate and a line extending along a channel length direction, and is inclined by seven degrees or more with respect to the line vertical to the principal surface of the semiconductor substrate, thereby forming second source/drain diffusion layers of the second conductivity type having a junction depth deeper than a junction depth of the first source/drain diffusion layers and making a length of the second source diffusion layer of the second conductivity type along the channel length direction shorter than a length of the second drain diffusion layer of the second conductivity type along the channel length direction.
In one embodiment, the method for fabricating a MOS type semiconductor device further includes a step of implanting ion seeds of the second conductivity type from drain side into the semiconductor substrate by using the gate electrode and the side wall spacers as a mask in a plane including a line vertical to the principal surface of the semiconductor substrate and a line extending along a channel length direction, and is inclined by seven degrees or more with respect to the line vertical to the principal surface of the semiconductor substrate. In this method, an implant dose from the source side is larger than an implant dose from the drain side.
In another embodiment, a diffusion layer in which an impurity concentration is nonuniform along the channel length direction is formed by implanting ion seeds of the second conductivity type from a source side into the semiconductor substrate by using the gate electrode as a mask in a plane including a line vertical to the principal surface of the semiconductor substrate and a line extending along the channel length direction, and is inclined by seven degrees or more with respect to the line vertical to the principal surface of the semiconductor substrate after performing the step of forming the gate electrode and before performing the step of forming the side wall spacers.
In still another embodiment, ion seeds of the first conductivity type are implanted by using the gate electrode as a mask after performing the step of forming the gate electrode and before performing the step of forming the side wall spacers, thereby forming a diffusion layer of the first conductivity type under the first source/drain diffusion layers having a shallow junction depth.
In still another embodiment, after performing the step of etching the first insulating film by photolithography and anisotropic etching until the first insulating film is exposed for forming the gate electrode, a step of implanting ion seeds of the first conductivity type from a source side into the semiconductor substrate by using the gate electrode as a mask in a plane which is vertical to the principal surface of the semiconductor substrate and is parallel to the channel length direction, and is inclined by seven degrees or more with respect to the line vertical to the principal surface of the semiconductor substrate is performed, and a diffusion layer for controlling a threshold potential, the impurity concentration of the diffusion layer being asymmetric along the channel length direction, and diffusion layers of the second conductivity type under the first source/drain diffusion layers having a shallow junction depth are simultaneously formed.
The MOS type semiconductor device according to still another aspect of the present invention includes: a semiconductor layer of a first conductivity type; a substrate for supporting the semiconductor layer; a source diffusion layer of a second conductivity type formed in a principal surface region of the semiconductor layer; a drain diffusion layer of the second conductivity type formed in the principal surface region of the semiconductor layer so as to be distant from the source diffusion layer; a channel region formed in the semiconductor layer so as to be located between the source diffusion layer and the drain diffusion layer; a gate insulating film provided on the channel region; a gate electrode provided on the gate insulating film; and an impurity diffusion layer of the first conductivity type which is formed in the channel region, and has a nonuniform impurity concentration profile along a channel length direction, an impurity concentration in a portion of the impurity diffusion layer which is adjacent to the source diffusion layer being higher than an impurity concentration in a portion of the impurity diffusion layer which is adjacent to the drain diffusion layer. In the semiconductor device, an impurity concentration of the semiconductor layer just under the source diffusion layer is lower than an impurity concentration on a source side of the impurity diffusion layer of the first conductivity type.
In one embodiment, the substrate is a substrate having an insulating surface.
In another embodiment, the substrate is a semiconductor substrate having an insulating film on a surface thereof, and the semiconductor layer is formed of an epitaxial layer formed on the insulating film on the surface of the semiconductor substrate.
Thus, the invention described herein makes possible the advantage of providing a highly reliable high-speed semiconductor device having large resistance to the short-channel effect, and a method for fabricating the same.